1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a high-voltage MOSFET, a low-voltage MOSFET, and an electrostatic protection MOSFET. In addition, the present invention relates to a method for producing the semiconductor device.
2. Description of the Related Art
In general, a semiconductor IC (Integrated Circuit) is vulnerable to a surge voltage generated by an electrostatic discharge (ESD), and likely to be broken down. Therefore, a circuit for electrostatic protection is normally provided in the IC to protect the IC from the surge voltage.
A circuit for electrostatic protection using an MOSFET is proposed as one example. For example, according to a circuit example shown in FIG. 6, an N-type MOSFET 91 is provided as an electrostatic protection circuit, and it is connected to an internal circuit 92 to be protected in parallel. In the N-type MOSFET 91, a source and a gate are short-circuited, and an off state is maintained under the condition that a normal signal voltage Vin is applied to a signal line SE in a normal time. However, when an excessive voltage Vsur which is considerably higher than the Vin is applied to the signal line SE, a pn junction between a drain of the N-type MOSFET 91 and a substrate is inversely biased, and a breakdown is caused. At this time, collisional ionization is caused just under the drain, and many holes are generated, so that a potential of the substrate rises. At the same time, many electrons are diffused from the source to the substrate, and a diffusion current is generated. This diffusion current turns on a parasitic bipolar transistor in which the drain serves as a collector, the source serves as an emitter, and the semiconductor substrate serves as a base (snapback phenomenon). As a result, the excessive voltage Vsur applied to the drain can be discharged to a ground line VSS connected to the source through the parasitic bipolar transistor. Therefore, since a large current derived from the excessive voltage Vsur does not flow in the internal circuit 92, the internal circuit 92 can be protected.
An increase in parasitic resistance (contact resistance) due to a fine processing technology hinders the speeding up of the IC. As a measure of this, the parasitic resistance must be reduced by a salicide (Self Aligned Silicide) technology.
The salicide technology is a technology to form a thermally reactive layer (salicide) of metal and silicon on a source/drain region and a gate electrode of a MOSFET in a self-aligned manner. After reaction between metal and silicon, its resistance value can be lowered as compared with that of a normal silicon layer or polysilicon layer.
However, this salicide technology could adversely affect function fulfillment of the electrostatic protection circuit to implement electrostatic protection by use of the MOSFET provided after the snapback phenomenon.
FIG. 7 is a conceptual diagram showing a relationship between a drain voltage Vd and a drain current Id in an N-type MOSFET after broken down. As the drain voltage increases, the MOSFET is broken down at a breakdown voltage Va, and a parasitic bipolar transistor is turned on, that is, the snapback phenomenon occurs. At this time, a negative resistance region in which the drain voltage Vd and the drain current Id have a negative correlation is generated (refer to <I> in the drawing). Thus, after the snapback phenomenon, a resistance region in which the drain voltage Vd and the drain current Id have a positive correlation is formed (refer to <II> in the drawing).
When a silicide layer is not formed on the source/drain region, as shown by a solid line (a) in FIG. 7, a slope of Id-Vd curve is small in the positive resistance region. This is derived from a resistance component in the source/drain region. Meanwhile, when the silicide layer is formed on the source/drain region, a resistance value in this region is largely lowered. Therefore, as shown by a broken line (b), a slope of Id-Vd curve is steep as compared with the line (a).
Therefore, in the case where the silicide layer is formed in the source/drain region of the electrostatic protection MOSFET 91, when the excessive Vsur is applied to the signal line SE, and the snapback phenomenon is generated, a considerably large current flows in the MOSFET 91 because its resistance value is small as compared with the case where the silicide layer is not formed. Thus, considerably high Joule heat is generated, and the MOSFET 91 is likely to be broken down. Once the MOSFET 91 is broken down, it does not serve to protect the internal circuit 92 anymore. That is, the problem is that the protection function for the internal circuit 92 is lowered because the MOSFET 91 is likely to be broken down.
In addition, in a case of a structure in which a drift region is provided outside the gate electrode in a high-voltage MOSFET, since a resistance value of the drift region is lowered due to the silicide layer, the drift region does not serve to relax an electric field. Therefore, in the case where the salicide technology and the high-voltage MOSFET are combined, a structure in which the drift region is formed under the gate electrode, that is, “gate-overlap structure” has been conventionally used.
However, this structure has the problem that capacitance between the gate and drain, or capacitance between the gate and source increases, which is disadvantageous to the high-speed operation, or the problem that a leak current flowing from the drain to the substrate called a GIDL (Gate Induced Leakage) increases because a gate electrode edge comes close to a silicide region or to the high concentration source/drain region.
In order to solve the above problems, a high-voltage MOSFET in which the silicide layer is not formed in a predetermined region while the drift region is provided outside the gate electrode, is proposed (refer to Japanese Patent Application Laid-Open Publication No. Hei 5-3173 (hereinafter, referred to as the document 1), and Japanese Patent Application Laid-Open Publication No. 2004-47721 (hereinafter, referred to as the document 2), for example).
FIGS. 8A and 8B are schematic cross-sectional views of a semiconductor device disclosed in the document 1, showing cross-sectional views at certain steps in the middle of manufacturing process for convenience of description. Regions B1 and B2 each partitioned by an element isolation region 101 are formed on a semiconductor substrate 100, and a MOSFET 121 serving as an element to be protected is formed in the region B1, and an electrostatic protection MOSFET 122 is formed in the region B2.
As shown in FIG. 8A, in the MOSFET 121, silicide layers 107 and 108 are formed on an upper surface of a low concentration diffusion region 103 and on an upper surface of a gate electrode 105, respectively. In addition, a sidewall insulation film 106 is formed on side walls of the gate electrode 105 and the silicide layer 108. In addition, reference 104 represents a gate oxide film.
In the electrostatic protection MOSFET 122 also, silicide layers 117 and 118 are formed on an upper surface of a low concentration diffusion region 113, and on an upper surface of the gate electrode 115, respectively. However, it is to be noted that the diffusion region 113 is not completely covered with the silicide layer 117, and a part of the region on the side of the gate electrode 115 is not covered with the silicide layer 117. That is, a separation region (X1) is provided between the silicide layer 117 and the gate electrode 115 in a horizontal direction. In addition, reference 114 represents a gate oxide film, and a reference 116 represents a sidewall insulation film, in the MOSFET 122.
In order to implement the above configuration, an insulation film (silicide block) 120 is previously formed in a region in which the silicide layer 117 is not to be formed, in a stage before the silicide layer 117 is formed, and silicide is formed in this state. Thus, silicide can be formed only in a part of the diffusion region 113.
In addition, in actual steps, the silicide layer 108 and the silicide layer 118 are formed at the same time, and then the insulation film 120 is formed and then the silicide layer 107 and the silicide layer 117 are formed at the same time As one example, the silicide layer 108 and the silicide layer 118 are formed of tungsten silicide, and the silicide layer 107 and the silicide layer 117 are formed of titanium silicide.
Then, as shown in FIG. 8B, after removing the insulation film 120, a high concentration impurity ion implantation is performed to form high concentration diffusion regions (source/drain regions) 102 and 112, and to dope the gate electrodes 105 and 115 with an impurity. Thus, while the source/drain region 102 is completely covered with the silicide layer 107 in the MOSFET 121, the region (X1) which is not covered with the silicide layer 117 is provided in the source/drain region 112, in the MOSFET 122 serving as the protection element. Thus, the resistance value after the snapback phenomenon can be prevented from being considerably lowered.
FIGS. 9A and 9B are schematic cross-sectional views of a configuration disclosed in the document 2, showing cross-sectional views at certain steps in the middle of manufacturing process for convenience of description. In addition, an electrostatic protection MOSFET is only shown in FIGS. 9A and 9B.
An element isolation region 201, a gate oxide film 204, and a gate electrode 205 are formed on a semiconductor substrate 200, and then a low concentration ion implantation is performed. By this ion implantation, a low concentration region 202 is formed on the side of a source, and a low concentration region 203 serving as an LDD region is formed on the side of a drain. Then, a sidewall insulation film 208 is formed and then a high concentration ion implantation is performed using a resist pattern 220 as shown in FIG. 9A. By this ion implantation, a drain 206 is formed in the low concentration region 203 away from an edge of the gate electrode 205 by a distance X2 in a horizontal direction. At this time, a source 207 is formed and an impurity is doped into the gate electrode 205 in the same step.
Then, the resist pattern 220 is removed, and as shown in FIG. 9B, an insulation film 212 serving as a silicide block is formed using a patterning shape having openings in an upper surface of the drain 206, an upper surface of the source 207, and a part of an upper surface of the gate electrode 205, and then silicide is formed. Thus, silicide layers 209, 210, and 211 are formed on an upper layer of the drain 206, an upper layer of the source 207, and an upper layer of the gate electrode 205, respectively.
In this case also, similar to FIGS. 8A and 8B, since the diffusion region 203 which is not covered with the silicide layer is formed in the separation region X2, a resistance value after the snapback phenomenon is prevented from being largely lowered.
However, according to the method described in the document 1, it is necessary to form silicide in twice, and it is necessary to separately form the insulation film 120 for blocking silicide, so that the number of steps and manufacturing cost largely increase.
In addition, according to the method described in the document 2, it is necessary to separately form the insulation film 212 for blocking silicide, so that the number of steps and manufacturing cost largely increase. In addition, the insulation film 212 needs to be aligned so as not to cover the already formed drain region 206, that is, it is not formed in a self-aligned manner. Therefore, it is necessary to ensure an alignment margin for the alignment, which causes increase in transistor size.